What’s New: At Hot Chips 34, Intel highlights the latest architectural and packaging innovations enabling the 2.5D and 3D tile-based chip designs that will bring about a new era in chipmaking and propel Moore’s Law forward for years to come. In Intel’s first Hot Chips CEO keynote since Gordon Moore’s in 1995, Intel CEO Pat Gelsinger shared the company’s path for continuing its relentless pursuit of more powerful compute, providing details from across the company’s upcoming portfolio, including Meteor Lake, Ponte Vecchio GPU, Intel® Xeon® D-2700 and 1700, and FPGAs, and outlining its new systems foundry model.

Why It Matters: The industry is entering a new golden age of semiconductors – an era in chipmaking that requires a shift from the traditional foundry model mindset to a systems foundry. Beyond supporting traditional wafer manufacturing, Intel’s systems foundry model incorporates advanced packaging, an open chiplet ecosystem and software components, to assemble and deliver systems in a package that meet the world’s insatiable demand for compute power and fully immersive digital experiences. Intel is also addressing industry demand with continued advances in process technology and tile-based design.

In this era of innovation, growth and discovery, technology will fundamentally alter how we experience the world. The ubiquity of compute, connectivity, infrastructure and AI will continue to create powerful new possibilities as they combine, amplify and reinforce each other, shaping the future of technology and enabling new levels of human achievement.

How Intel is Doing It: Intel previewed the following product architectures from next-generation technologies at Hot Chips 34:  

• Meteor Lake, Arrow Lake and Lunar Lake processors will transform personal computers with tile-based chip designs that create efficiencies in manufacturing, power and performance. This is done through discrete CPU, GPU, SoC and I/O tiles stacked in 3D configurations using Intel’s Foveros interconnect technology. This platform transformation is reinforced by industry support for the open Universal Chiplet Interconnect Express (UCIe™) specification enabling chiplets designed and manufactured on different process technologies by different vendors to work together when integrated with advanced packaging technologies.
• Intel Data Center GPU, code-named Ponte Vecchio, was built to address the compute density across high performance computing (HPC) and AI supercomputing workloads. It also takes full advantage of Intel’s open software model, using OneAPI to simplify API abstractions and cross-architecture programming. Ponte Vecchio is composed of several complex designs that manifest in tiles, connected using a combination of embedded multi-die interconnect bridge (EMIB) and Foveros advanced packaging technologies. The high-speed MDFI interconnect allows the package to scale up to two stacks, allowing a single package to contain more than 100 billion transistors.
• Xeon D-2700 and 1700 series are designed to address edge use cases for 5G, IoT, enterprise and cloud applications, with special consideration to the power and space constraints that are common in many real-world implementations. These chips are also examples of tile-based design, including state-of-the-art compute cores, 100G Ethernet with flexible packet processor, inline crypto acceleration, time coordinated computing (TCC), time-sensitive networking (TSN) and built-in optimization for AI processes.
• FPGA technology continues to be a powerful and flexible tool for hardware acceleration, with particular promise for radio frequency (RF) applications. Intel has identified new efficiencies by integrating digital and analog chiplets, as well as chiplets from different process nodes and foundries, cutting development time and maximizing flexibility for developers. Intel will share the results of its chiplet-based approach in the near future.